CVE-2025-0647
HighSummary
In certain Arm CPUs, executing a CPP RCTX instruction on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to that PE, either by the same PE or another PE in the shareability domain. As a result, the PE may retain stale TLB entries that should have been invalidated by the TLBI.
Risk Assessment
The risk is that the system may use stale address translations, potentially leading to memory isolation breaches, unauthorized data access, or system inconsistencies.
Recommendation
Apply patches provided by the CPU or operating system vendor that address the TLB invalidation issue. Also monitor Arm and platform vendor security advisories.
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Original NVD description (English source)
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.