CVE Catalog

CVE-2026-98546

Low risk· EPSS 9%
Published: Updated: Translated: NVD NIST

Exploitation Probability (EPSS)

Low risk
0.20%

9th percentile - higher than 9% of all known CVEs

Summary

In the Linux kernel, __init_el2_fgt2() wrote the same mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2, so the nPMZR_EL0 trap bit for PMZR_EL0 writes was never set. With kernel.perf_user_access=1, a PMZR_EL0 write from EL0 traps to EL2, where the nVHE hypervisor has no handler and BUG()s, taking the host down without a panic message.

Risk Assessment

A host hang or crash (DoS) can be triggered by a PMZR_EL0 write from userspace when kernel.perf_user_access=1 is enabled. Affects arm64 systems with the nVHE hypervisor.

Recommendation

Update the Linux kernel to a version containing the fix that accumulates HDFGWTR2_EL2 bits separately and sets nPMZR_EL0 along with the other FEAT_PMUv3p9 bits.

Other vulnerabilities in Linux kernel

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Original NVD description (English source)

In the Linux kernel, the following vulnerability has been resolved: arm64/boot: Disable trapping of PMZR_EL0 writes to EL2 __init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2. PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a write from EL0 reaches the trap and takes the host down without a panic message. Accumulate the HDFGWTR2_EL2 bits separately, as __init_el2_fgt() already does for HDFGWTR_EL2, and set nPMZR_EL0 with the other FEAT_PMUv3p9 bits.

Vulnerability data from NVD (NIST) · CISA KEV · EPSS