CVE-2026-97587
UnknownSummary
In the Linux kernel, the RISC-V perf subsystem stored the available-counter mask as a single unsigned long, but iteration uses RISCV_MAX_COUNTERS which is 64. On RV32 this reads past the object, and setting an unsigned-long bit at index 32 and above is also wrong.
Risk Assessment
Out-of-bounds reads and incorrect bit operations may lead to kernel crashes or incorrect performance counter behavior on 32-bit RISC-V systems.
Recommendation
Update the Linux kernel to a version containing the fix that uses DECLARE_BITMAP and set_bit/bitmap helpers.
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Original NVD description (English source)
In the Linux kernel, the following vulnerability has been resolved: perf: RISC-V: store available counter mask as bitmap The available-counter mask was a single unsigned long, but iteration uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object. Filling with an unsigned-long bit at index 32 and above is also wrong. Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word into CFG_MATCH when checking events, when allocating an index, and when stopping all counters. Set the counter base to i times BITS_PER_LONG. Share the CFG_MATCH ecall through a small helper so the 32-bit argument split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits above XLEN set, so the first word alone is not enough. [[email protected]: updated to apply; fixed checkpatch.pl issues]
Vulnerability data from NVD (NIST) · CISA KEV · EPSS