CVE Catalog

CVE-2026-90410

Low risk· EPSS 11%
Published: Updated: Translated: NVD NIST

Exploitation Probability (EPSS)

Low risk
0.21%

11th percentile - higher than 11% of all known CVEs

Summary

In the Linux kernel, the spi-davinci driver allocates the controller with spi_alloc_host() but registers the interrupt with devm_request_threaded_irq(). During removal, the controller is freed before the IRQ handler is drained, allowing a late interrupt to dereference freed memory. The fix switches to devm_spi_alloc_host() and explicitly drains the interrupt with devm_free_irq().

Risk Assessment

A use-after-free in interrupt context can lead to kernel crashes or potential privilege escalation. This affects systems with the Davinci SPI controller, mainly embedded platforms.

Recommendation

Update the Linux kernel to a version containing the spi-davinci fix. Avoid dynamically removing and reloading the driver module until the update is applied.

Related vulnerabilities

Original NVD description (English source)

In the Linux kernel, the following vulnerability has been resolved: spi: davinci: switch to managed controller allocation The controller is allocated with the non-managed spi_alloc_host() while the interrupt is registered with devm_request_threaded_irq(). During removal, spi_bitbang_stop() only unregisters the controller; the subsequent spi_controller_put() then frees the controller together with its embedded davinci_spi devdata, which is the IRQ handler's dev_id. The devm_request_threaded_irq() release action (free_irq()), which drains the handler, does not run until after .remove() returns. A late or latched interrupt can therefore reach davinci_spi_irq() and dereference already-freed memory. Switch to devm_spi_alloc_host() so that the devres LIFO order releases the controller only after free_irq() has drained the handler, and drop the now-redundant spi_controller_put() from .remove(). The probe error path is simplified to direct returns. The clock is acquired with devm_clk_get_enabled(), which is registered after the IRQ and thus released before it by the devres LIFO order. Drain the interrupt explicitly with devm_free_irq() before disabling the controller so that a late interrupt cannot access the registers of a clock-gated controller. This issue was found by an in-house static analysis tool.

Vulnerability data from NVD (NIST) · CISA KEV · EPSS