CVE-2026-74276
Low risk· EPSS 7%Exploitation Probability (EPSS)
Low risk7th percentile - higher than 7% of all known CVEs
Summary
A vulnerability was found in the Linux kernel's SPI driver for Xilinx devices. The driver incorrectly determines the FIFO buffer size, not accounting for the shift register, which leads to data loss and driver looping during SPI transfers in interrupt mode.
Risk Assessment
The vulnerability can cause the driver to hang (infinite loop), leading to system unresponsiveness or failure of SPI-connected devices. In extreme cases, it may allow a DoS attack on the system.
Recommendation
Apply the patch provided by the Linux kernel maintainers immediately. Update the kernel to a fixed version or backport the fix to your current kernel version.
Other vulnerabilities in Linux kernel
See all- CVE-2026-99259Unknown
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- CVE-2026-99258Unknown
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- CVE-2026-99257Unknown
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- CVE-2026-99256Unknown
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- CVE-2026-99251Unknown
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- CVE-2026-99250Unknown
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- CVE-2026-99249Unknown
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- CVE-2026-99248Unknown
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- CVE-2026-99247Unknown
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- CVE-2026-99215Unknown
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Original NVD description (English source)
In the Linux kernel, the following vulnerability has been resolved: spi: xilinx: use FIFO occupancy register to determine buffer size The method the driver uses to determine the size of the FIFO has a problem. What it currently does is this: It stops the SPI hardware and writes to the TX FIFO register until TX FIFO FULL asserts in the status register. But the hardware does not only have the FIFO, it also has a shift register which can hold a byte. This can be seen, when writing a byte to the FIFO (while the SPI hardware is stopped,) the TX FIFO EMPTY is still empty. So, if we have a FIFO size of 16 for example, the current method returns a 17. This is a problem, at least when using the driver in irq mode. The same size determined for the TX FIFO is also assumed for the RX FIFO. When a SPI transaction wants to write the amount of the FIFO size or more bytes, the following happens, for example with 16 bytes FIFO size: The driver stops the SPI hardware and writes 17 bytes to the TX FIFO and starts the SPI hardware and goes sleep. The hardware then shifts out 17 bytes (FIFO + shift register) and simultaneously reads bytes into the RX FIFO, but it only has 16 places, so it looses one byte. Then TX FIFO empty asserts, wakes the driver again, which has a fast path and reads 16 bytes from the RX FIFO, but before reading the last 17th byte (which is lost) it does this: sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); if (!(sr & XSPI_SR_RX_EMPTY_MASK)) { xilinx_spi_rx(xspi); rx_words--; } It reads the status register and checks if the RX FIFO is not empty. But it is empty in our case. So this check spins in a while loop forever locking the driver. This patch fixes the logic to determine the FIFO size.
Vulnerability data from NVD (NIST) · CISA KEV · EPSS