CVE Catalog

CVE-2026-63875

HighCVSS 7.8
Published: Updated: Translated: NVD NIST

Exploitation Probability (EPSS)

Low risk
0.16%

6th percentile - higher than 6% of all known CVEs

Summary

In the Linux kernel for ARM64 architecture, a vulnerability was found in the TLB walk cache invalidation mechanism. The tlb_flush() function did not check the unshared_tables flag, causing the wrong instruction (VALE1IS instead of VAE1IS) to be used after PMD table unsharing (huge_pmd_unshare), leaving stale non-leaf entries in the walk cache. This could lead to incorrect page table walks.

Risk Assessment

The risk involves potential memory integrity violations and system instability. Incorrect address translations may cause read/write to wrong memory areas, kernel panics, or in extreme cases privilege escalation.

Recommendation

Immediately update the Linux kernel to a version containing the fix (commit correcting the condition in tlb_flush() for ARM64). Monitor kernel distributions and apply the security patch.

Other vulnerabilities in Linux kernel

See all
Original NVD description (English source)

In the Linux kernel, the following vulnerability has been resolved: arm64: tlb: Flush walk cache when unsharing PMD tables When huge_pmd_unshare() is called to unshare a PMD table, the tlb_unshare_pmd_ptdesc() function sets tlb->unshared_tables=true but the aarch64 tlb_flush() only checked tlb->freed_tables to determine whether to use TLBF_NONE (vae1is, invalidates walk cache) or TLBF_NOWALKCACHE (vale1is, leaf-only). This caused the stale PMD page table entry to remain in the walk cache after unshare, potentially leading to incorrect page table walks. Fix by including unshared_tables in the check, so that when unsharing tables, TLBF_NONE is used and the walk cache is properly invalidated. Here is the detailed distinction between vae1is and vale1is: | Instruction Combination | Actual Invalidation Scope | | ------------------------ | --------------------------------------------------| | `VAE1IS` + TTL=`0` | All entries at all levels (full invalidation) | | `VAE1IS` + TTL=`2` (L2) | Non-leaf at Level 0/1 + leaf at Level 2 | | `VALE1IS` + TTL=`0` | Leaf entries at all levels (non-leaf not cleared) | | `VALE1IS` + TTL=`2` (L2) | Leaf entry at Level 2 only |

Vulnerability data from NVD (NIST) · CISA KEV · EPSS