CVE Catalog

CVE-2026-23361

HighCVSS 7.8
Published: Updated: Translated: NVD NIST

Exploitation Probability (EPSS)

Low risk
0.17%

6th percentile - higher than 6% of all known CVEs

Summary

In the Linux kernel PCI dwc ep driver, a race exists between the MSI-X write (writel) and unmapping of the ATU entry. Since PCI posted writes have no completion, the write may not reach the destination before the unmap, potentially corrupting host memory or causing IOMMU errors. The fix performs a readl of the same address to flush the write before unmapping the ATU entry.

Risk Assessment

The vulnerability can lead to host memory corruption or IOMMU errors (e.g., F_TRANSLATION) during MSI-X interrupt handling, potentially causing system instability or data loss. It affects environments using DWC PCIe controllers in endpoint mode with MSI-X.

Recommendation

Update the Linux kernel to a version containing the fix for CVE-2026-23361. If updating is not possible, limit MSI-X usage in endpoint drivers or monitor IOMMU logs for translation faults.

Other vulnerabilities in Linux kernel

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Original NVD description (English source)

In the Linux kernel, the following vulnerability has been resolved: PCI: dwc: ep: Flush MSI-X write before unmapping its ATU entry Endpoint drivers use dw_pcie_ep_raise_msix_irq() to raise an MSI-X interrupt to the host using a writel(), which generates a PCI posted write transaction. There's no completion for posted writes, so the writel() may return before the PCI write completes. dw_pcie_ep_raise_msix_irq() also unmaps the outbound ATU entry used for the PCI write, so the write races with the unmap. If the PCI write loses the race with the ATU unmap, the write may corrupt host memory or cause IOMMU errors, e.g., these when running fio with a larger queue depth against nvmet-pci-epf: arm-smmu-v3 fc900000.iommu: 0x0000010000000010 arm-smmu-v3 fc900000.iommu: 0x0000020000000000 arm-smmu-v3 fc900000.iommu: 0x000000090000f040 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 arm-smmu-v3 fc900000.iommu: event: F_TRANSLATION client: 0000:01:00.0 sid: 0x100 ssid: 0x0 iova: 0x90000f040 ipa: 0x0 arm-smmu-v3 fc900000.iommu: unpriv data write s1 "Input address caused fault" stag: 0x0 Flush the write by performing a readl() of the same address to ensure that the write has reached the destination before the ATU entry is unmapped. The same problem was solved for dw_pcie_ep_raise_msi_irq() in commit 8719c64e76bf ("PCI: dwc: ep: Cache MSI outbound iATU mapping"), but there it was solved by dedicating an outbound iATU only for MSI. We can't do the same for MSI-X because each vector can have a different msg_addr and the msg_addr may be changed while the vector is masked. [bhelgaas: commit log]

Vulnerability data from NVD (NIST) · CISA KEV · EPSS