CVE-2026-12629
MediumCVSS 4.6Exploitation Probability (EPSS)
Low risk6th percentile - higher than 6% of all known CVEs
Summary
The ARM PL011 UART driver (drivers/serial/uart_pl011.c) fails to acknowledge receive error interrupts. Framing, parity, break, and overrun errors are cleared only by writing the UARTICR register, but the interrupt service routine pl011_isr() does not do this, leaving the interrupt pending. An attacker controlling the serial peer can trigger these errors, causing an interrupt storm and permanent system hang.
Risk Assessment
The risk is a denial of service (permanent hang) reachable from an external or removable UART peer, but only if an application explicitly enables error-interrupt reporting via uart_irq_err_enable(). An attacker can inject line errors, causing the CPU to make no forward progress and making the system unavailable.
Recommendation
Apply the vendor patch that makes pl011_isr() acknowledge pending error bits via uart->icr and clears the latched RSR status in pl011_err_check(). If the patch is unavailable, avoid using uart_irq_err_enable() on PL011 ports or disable error interrupts in configuration.
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- CVE-2026-80533Unknown
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Original NVD description (English source)
The ARM PL011 UART driver in drivers/serial/uart_pl011.c fails to acknowledge receive error interrupts. On the PL011, the framing, parity, break, and overrun error interrupts (PL011_IMSC_ERROR_MASK) are cleared only by writing the interrupt-clear register UARTICR; reading the data register clears the RX interrupt and the per-byte RSR status but not the error interrupt status in MIS. The interrupt service routine pl011_isr() acknowledged only the CTS modem-status interrupt and never wrote icr for the error bits, so an asserted error interrupt remains pending after the ISR returns. When an application enables error-interrupt reporting via the public uart_irq_err_enable() API, an attacker who controls the serial peer can deterministically assert these error bits by injecting line errors on the RX line — a baud/stop-bit mismatch or mid-character break (framing/break error), a flipped parity bit (parity error), or FIFO flooding (overrun error). Because the error interrupt is never cleared, the interrupt line stays asserted and the CPU re-enters pl011_isr() immediately and indefinitely, producing an interrupt-storm livelock from which the core makes no forward progress. The impact is an availability-only denial of service (permanent hang), reachable from an external or removable UART peer. Exploitation is gated by configuration: the error interrupt is off by default and no in-tree subsystem enables it, so only applications that explicitly call uart_irq_err_enable() on a PL011-based, interrupt-driven port are affected. The fix makes pl011_isr() acknowledge the pending error bits via uart->icr, breaking the loop, and additionally clears the latched RSR status in pl011_err_check().