CVE Catalog

CVE-2026-10679

LowCVSS 3.3
Published: Updated: Translated: NVD NIST

Exploitation Probability (EPSS)

Low risk
0.13%

3th percentile - higher than 3% of all known CVEs

Summary

In the DesignWare SPI driver (drivers/spi/spi_dw.c) in Zephyr up to v4.4.0, lack of validation of config->frequency allows an unprivileged thread with access to the SPI device to trigger an unsigned integer divide-by-zero. This causes a CPU exception and local denial of service. Requires CONFIG_USERSPACE=y and granted permissions.

Risk Assessment

An attacker with an unprivileged thread can cause a kernel fault and local denial of service, potentially disrupting IoT devices.

Recommendation

Update Zephyr to a version above v4.4.0 that includes the fix rejecting zero frequency. Restrict access to the SPI driver.

Other vulnerabilities in Zephyr

See all
Original NVD description (English source)

The DesignWare SPI driver (drivers/spi/spi_dw.c) computed the SPI BAUDR clock divider as info->clock_frequency / config->frequency without validating config->frequency. spi_transceive is a Zephyr __syscall and its verify handler (drivers/spi/spi_handlers.c) copies the caller-supplied spi_config from userspace without checking the frequency field, so a userspace thread that has been granted access to a DesignWare SPI device kernel object can pass frequency = 0 and trigger an unsigned integer divide-by-zero in spi_dw_configure(). On Cortex-M Mainline (SCB->CCR.DIV_0_TRP is set in z_arm_fault_init()) and on ARC (a dedicated __ev_div_zero vector) this raises a CPU exception, resulting in a kernel fault and local denial of service. The fix rejects zero frequency and frequencies above clock_frequency / 2 (the DesignWare SSI databook minimum SCKDIV of 2) with -EINVAL. The defect affects all Zephyr releases up to and including v4.4.0; exploitation requires CONFIG_USERSPACE=y and an unprivileged thread already granted SPI driver permission. There is no memory-corruption or information-disclosure impact.

Vulnerability data from NVD (NIST) · CISA KEV · EPSS