CVE-2025-40174
HighCVSS 7.8Exploitation Probability (EPSS)
Low risk3th percentile - higher than 3% of all known CVEs
Summary
In the Linux kernel on x86, switch_mm_irqs_off() lacks a memory barrier (smp_mb()) between the loaded_mm store and the tlb_gen load. This can cause context switching to miss a tlb_gen update and fail to flush TLBs, leading to stale data usage.
Risk Assessment
The organization risks memory consistency errors, potentially causing system crashes or security breaches via access to stale pages.
Recommendation
Update the Linux kernel to a version containing the fix for CVE-2025-40174.
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Original NVD description (English source)
In the Linux kernel, the following vulnerability has been resolved: x86/mm: Fix SMP ordering in switch_mm_irqs_off() Stephen noted that it is possible to not have an smp_mb() between the loaded_mm store and the tlb_gen load in switch_mm(), meaning the ordering against flush_tlb_mm_range() goes out the window, and it becomes possible for switch_mm() to not observe a recent tlb_gen update and fail to flush the TLBs. [ dhansen: merge conflict fixed by Ingo ]

